1. Field
The present embodiment relates to a clock buffer, and particularly to a clock buffer for waveform-shaping a clock.
2. Description of the Related Art
Recently, the speed of signal transmission between circuit blocks in chips, between LSI (Large Scale Integration) chips, between circuit boards or between chassis is more and more increased. Accompanying this tendency, the performance of components constituting computers and information processing apparatuses has been greatly improved. For example, improvements in the performance of SRAMs (Static Random Access Memories), DRAMs (Dynamic Random Access Memories), processors and switching LSIs have been made. As a result, there causes a problem that system performance cannot be further improved unless the speed of signal transmission between components or elements is increased.
Specifically, the speed gap between memories such as SRAMs and DRAMs and processors tends to widen, and this speed gap is recently becoming a hindrance to the performance improvement of computers. Further, with the increase in size of chips, not only the speed of signal transmission between these chips but also the speed of signal transmission between elements or circuit blocks in chips has become a major factor limiting the performance of chips. Moreover, the speed of signal transmission between peripheral devices and the processor/chipset has also become a factor limiting the performance of the whole system.
In speeding up the signal transmission between circuit blocks, between chips or between chassis, it is essential to propagate a high-speed clock to the circuit block without deteriorating clock quality (skew, jitter amount). The reason is that the timing accuracy of the propagated clock affects the accuracy of receive timing and also the timing accuracy of a signal to be generated.
For clock transmission in LSIs, an unbalanced clock buffer using an inverter or a balanced clock buffer based on differential CML (Current Mode Logic) is conventionally used.
FIG. 26 is a circuit diagram of the unbalanced clock buffer using an inverter. The clock buffer shown in FIG. 26 comprises an inverter composed of a PMOS transistor M101 and an NMOS transistor M102.
FIG. 27 is a circuit diagram of a balanced clock buffer based on differential CML. The clock buffer shown in FIG. 27 comprises NMOS transistors M111 and M112 forming a differential input, a transistor M113 for causing a bias current to flow through the transistors M111 and M112, and resistors R101 and R102.
Each of the clock buffers shown in FIGS. 26 and 27 has a low-pass frequency characteristic, in which a cutoff frequency of the clock buffer is higher than a fundamental frequency of a clock to be transmitted and a gain at frequencies sufficiently below the fundamental frequency of the clock is 0 dB or more. This is for preventing that a waveform of the clock is attenuated so as not to be propagated.
FIG. 28 shows frequency characteristics of a conventional clock buffer. As shown in FIG. 28, the conventional clock buffer has a low-pass filter characteristic which passes signals below the cutoff frequency fc. The clock buffer is designed such that its cutoff frequency is higher than the fundamental frequency of a clock to be transmitted and a gain at low frequencies is 0 dB or more to prevent a voltage waveform of the clock from disappearing.
There is disclosed a solid-state image sensor drive circuit having simple circuitry which reduces power consumption of transfer type solid-state image sensor such as a CCD (Charged Coupled Device) and which enables a modulation of a transfer clock also at low frequencies (see, e.g., Japanese Unexamined Patent Application Publication No. 5-122625).
However, the conventional clock buffer has the following problems. First, since the gain at frequencies sufficiently below the fundamental frequency of a clock is 0 dB or more, when noise at frequencies below the fundamental frequency of the clock is added, the noise is amplified and the jitter is increased.
Further, when variations occur in elements constituting a clock buffer, for example, when differences occur between threshold voltages of differential input transistors, since the gain at low frequencies is 0 dB or more, an error voltage (offset voltage) produced by converting a threshold voltage difference to an input voltage difference is amplified and output as a differential output. Specifically, when a clock superimposed with a DC component passes through multiple stages of clock buffers, the DC component is amplified and as a result, the clock disappears.